Differences in HBM and MM test results

HBM and MM are important standards for ESD testing and typically correlate well. In some notable cases however, MM shows much lower failure levels than HBM. One of the most important physical mechanisms responsible for this is dynamic avalanching. This paper provides an example of such a dynamic avalanching failure, and includes a description of the physics involved. The correlation between HBM and MM test results is normally between 10 to 30, depending on the technology, meaning that 200V MM corresponds to 2kV to 4kV HBM. This correlation factor needs to be determined once for each technology, and can be reused for all other test cases. This correlation factor stems from the difference in peak current and induced energies of both models (Figure 1). Since the rise time of both models is comparable, this is a reasonable assumption. The bipolar nature of MM is slow enough such that for most cases the influence of the previous positive or negative swing can be neglected, reducing the physics to the unipolar case. Figure 1: MM and HBM pulse, the main difference being the bipolar characteristic of the MM pulse Figure 2: Diode up was destroyed by a positive MM stress between IO and VDD2. This is however, not a general statement. The most notable physical effect for which this simplification is not valid is dynamic avalanching. In Figure 2 a case is shown in which MM stress damaged a diode up, which can not be explained by merely looking at the peak current or energy dissipated by the MM pulse. The failure occurred at an MM stress of 160V MM between IO and Vdd; the diode survived 4 kV HBM. The technology is 13.5V 0.35um CMOS. (for a similar example, see [1]) Figure 3: Schematic representation, comparing the dynamic case (1a-3a) to the static case (1b-3b) for 3 different moments in time (a: Strong forward bias, b: zero bias, c: negative bias) Dynamic Avalanching is explained as follows (Figure 3) [2-8]. During the first positive MM swing, the diode is in forward mode, and the current is carried by the excess carriers (High Injection, Figure 3.1). As the current pulse turns negative, these excess carriers are still present in the diode bulk (Figure 3.2). The carriers contribute in the reverse avalanching, such that the avalanching is more severe for the same electrical field in the dynamic case as compared to the static case (Figure 3.3). This is called first degree of dynamic avalanching, which is typically non-destructive. A feedback mechanism is present to lower the voltage with higher currents: the excess carriers can be O. Marichal et al. – Abstract IEW 2007 – Differences in HBM and MM test results Sarnoff Europe confidential and proprietary 2006 For review by IEW symposium TPC only annihilated by the carriers created by the avalanching. This creates a small negative resistance regime, which is the signature of the second degree of dynamic avalanching. Although this causes some current filamentation, this is most often still not destructive, as it is counteracted by 2 other mechanisms: • The current filamentation can rapidly and locally deplete the bulk of the diode from excess carriers, such that the cause for the dynamic avalanching locally disappears • With the current filamentation, a hot spot is created. The avalanche voltage increases with temperature however, overcoming the negative resistance regime. Destruction is only likely when the third degree of Dynamic Avalanching is reached. The large current flowing causes the N+/Nwell junction to go into avalanche breakdown. The carriers thus generated increase the excess carriers in the bulk of the diode, therefore causing a positive feedback. The electrical field associated with this behavior is shown in Figure 4. Field peaks are observed both at the P+/Nwell and N+/Pwell junctions. This is called an “Egawa” field. Although this is figure is taken for a power diode, the physics is believed to be the same for this CMOS technology. Figure 4: Schematic representation of the electrical field (Solid line) during the third degree of dynamic avalanching Figure 5: formation of the depletion regions at different times [9] Dynamic Avalanching can thus explain why the diode up fails during MM, but not during HBM. In order to have a comprehensive understanding, it must also be explained why the same failure does not occur for the diode down, when putting a negative MM zap between IO and Vss. Consider the depletion region in figure 5. It can easily be seen that the depletion region grows much faster at the P+ side than at the N+ side. This is due to the difference in diffusion coefficient between holes and electrons. Thus, this behavior is the same for Nwell as for Pwell diodes. The electrical field however is built up over the PN junction. The voltage can change more rapidly in the depletion region than in the plasma region (i.e. the region with excess carriers). This gives rise to different behavior of both diode types: for the Nwell diode, the voltage built up is fast, as it is located at the rapidly growing P+/Nwell depletion region, such that the excess carriers will be swept through a large electrical field. For Pwell diodes, the voltage change is only moderately fast, because the N+/Pwell depletion region extends slower. Therefore, there is more time for the excess carriers to leave the bulk of the diode, without having to go through a large electric field.